This type of semiconductor integrated circuit, that is, LSI used as a timing controller (T-COM), etc., for a liquid crystal panel, etc., which corresponds to a liquid crystal display device as a display device processes an input image signal to generate a digital image signal and a control signal, and outputs the generated image signal and control signal to a driver IC of the liquid crystal panel, etc.
Recently, timing controllers have performed various controls, and controls have gradually become complicated. Therefore, as disclosed in Japanese Laid-Open Patent Publication No. 2003-139818, a bus interface (hereinafter referred to as bus I/F) as a control bus portion for processing predetermined signals, for example, a serial clock, serial data from the outside is provided in the timing controller.
For LSI such as the timing controller, as described above, a test for detecting faults occurring in the LSI due to a manufacturing failure, etc., is carried out.
As a result, the test method described above has been used as a method using a tester for inputting a test pattern for testing an LSI and comparing an output expected value to the input with an actual output result to test a data signal processor.
However, the transfer rate of a bus I/F, that is, the bus clock is generally remarkably slower than the transfer rate of a data signal processor for processing image data, that is, the system clock. For example, the system clock is approximately several tens of MHz, however, the bus clock is approximately 100 kHz. Accordingly, even when a test pattern is input at a high speed, the test pattern is not input to the data signal processor at a high speed, and thus approximately four million clocks as the system clock are required to renew all the control registers.
On the other hand, the length of the test pattern output from the tester is restricted, and it is limited to approximately 100,000 clocks as the system clock at a maximum.
Accordingly, with respect to the above LSI, there is a problem that the data signal processor cannot be controlled on the basis of the test pattern and it is impossible to sufficiently test an LSI.
The present invention has been made in view of the above points, and an object thereof is to provide a semiconductor integrated circuit that can be reliably tested, and a test method for the semiconductor integrated circuit.